Year 11 · Computer Science · Spring 2 – Summer 1

Final revision and the exams · Lesson 2 of 5

The most-missed questions, whole class

Exam practice3.1 Computer architecture2.2 Methods of error detection7.9 Writing and amending algorithms

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

You will learn to

  • Identify why most pupils lost marks on the five most-missed mock questions.
  • Write a full-mark answer to each question, using the mark-scheme words.
  • Explain the difference between your mock answer and the full-mark answer.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Success criteria

You have got it when you can say:

  • I can say what the examiner wanted in each of the five questions.
  • I can rewrite my own mock answer to earn full marks.
  • I can name one habit I will change in the final exam.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Retrieval starter

Questions from before. Write your answers, then show them.

  1. Last lesson

    Bubble sort stops when…

    A A whole pass makes no swapsB Half the list is sortedC The first swap happens

    A. A whole pass makes no swaps

  2. Last unit

    Abnormal test data is…

    A Data at the edge of the rangeB Typical dataC Data that should be rejected

    C. Data that should be rejected

  3. Earlier this year

    A solid-state drive…

    A Uses spinning plattersB Uses a laserC Has no moving parts

    C. Has no moving parts

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (1 of 9)

CPU
The central processing unit, which processes instructions and data by fetching, decoding and executing them.
Microprocessor
A CPU made as an integrated circuit on a single chip.
Von Neumann architecture
A computer design where instructions and data are stored together in the same memory.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (2 of 9)

ALU
Arithmetic logic unit: does calculations and logical comparisons.
Control unit
Manages the fetch–decode–execute cycle and sends control signals.
Register
A tiny, very fast store inside the CPU that holds one item.
Bus
A set of parallel wires that carries addresses, data or control signals.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (3 of 9)

Cache
Small, very fast memory in or near the CPU that holds frequently used data and instructions.
Clock speed
The number of cycles the CPU does each second, measured in hertz.
Core
A complete processing unit; a multi-core CPU can process several instructions at once.
Instruction set
The list of all the instructions a particular CPU can carry out.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (4 of 9)

Embedded system
A computer system inside a larger device that does one dedicated job.
Sensor
An input device that measures a physical property and sends the reading to a computer.
NIC
Network interface card: the hardware that connects a device to a network.
MAC address
A unique 48-bit address given to a NIC at manufacture, written in hex.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (5 of 9)

IP address
An address given to a device on a network so data can be sent to it.
Packet
A small piece of data sent across a network, with a header, payload and trailer.
Packet switching
Sending each packet separately, possibly by different routes, then reordering them at the destination.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (6 of 9)

Interference
Unwanted outside signals that can corrupt data on the way.
Parity bit
An extra bit that makes the number of 1s in a byte odd or even.
Checksum
A value calculated from a block of data, recalculated by the receiver to check for errors.
Echo check
The receiver sends the data back so the sender can compare it with the original.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (7 of 9)

Check digit
An extra digit calculated from the other digits, used to catch typing errors.
ARQ
Automatic repeat query: acknowledgements and timeouts make the sender re-send data that is wrong or lost.
Algorithm
A precise, ordered set of steps that solves a problem.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (8 of 9)

Program development life cycle
The four stages of making a program: analysis, design, coding and testing.
Structure diagram
A top-down diagram that shows how a system is split into sub-systems.
Pseudocode
A structured, code-like way of writing an algorithm that is not tied to one language.
Totalling
Adding values into a running total, for example Total ← Total + Value.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Key words (9 of 9)

Counting
Adding 1 to a counter each time something happens.
Bubble sort
Sorting by comparing neighbouring items and swapping them if they are in the wrong order, pass after pass.
Validation
An automatic check that input data is reasonable and follows set rules.

3.1 Computer architecture · The explanation · step 1 of 19 · part 1 of 2

The CPU and the microprocessor

The CPU (central processing unit) is the part of the computer that processes instructions and data. It carries out the instructions of every program.

It does this by fetching an instruction from memory, decoding it, then executing it. Then it repeats, billions of times a second.

A microprocessor is a CPU built as an integrated circuit on a single chip. An integrated circuit is a whole electronic circuit made on one small piece of silicon.

3.1 Computer architecture · The explanation · step 1 of 19 · part 2 of 2

The CPU and the microprocessor (continued)

e.g.Example
The chip inside a laptop, a phone or a games console is a microprocessor. A microprocessor also sits inside a microwave oven, running its timer.

3.1 Computer architecture · The explanation · step 2 of 19 · part 1 of 2

Von Neumann architecture

Most computers follow the von Neumann architecture. Its key idea is the stored program: instructions and data are both stored in the same main memory.

The CPU has a control unit (CU). The CU manages the fetch–decode–execute cycle. It decodes instructions and sends control signals to the other parts.

The CPU has an arithmetic logic unit (ALU). The ALU does calculations (such as add and subtract) and logic operations (such as comparing two numbers).

3.1 Computer architecture · The explanation · step 2 of 19 · part 2 of 2

Von Neumann architecture (continued)

The CPU also has registers: very small, very fast stores inside the CPU. The CPU is joined to memory by three buses (sets of wires).

?Why?

Keeping instructions and data in one memory means the computer can run any program you load. Change the program in memory and the same hardware does a new job.

There is a diagram for this step in the IGCSE library.

3.1 Computer architecture · The explanation · step 3 of 19 · part 1 of 2

The five registers

A register holds one item at a time: an address, an instruction or a piece of data.

An address is the number of a location in memory, like a locker number in a school corridor.

3.1 Computer architecture · The explanation · step 3 of 19 · part 2 of 2

The five registers (continued)

RegisterFull nameWhat it holds
PCProgram counterThe address of the next instruction to be fetched
MARMemory address registerThe address of the memory location about to be read from or written to
MDRMemory data registerThe data or instruction that has been fetched from memory, or about to be written to memory
CIRCurrent instruction registerThe instruction that is being decoded and executed right now
ACCAccumulatorThe result of calculations done by the ALU
!Watch out

PC and MAR hold addresses. MDR and CIR hold instructions or data. Mixing these up is the most common error in FDE answers.

3.1 Computer architecture · The explanation · step 4 of 19 · part 1 of 2

The three buses

The address bus carries addresses from the CPU (the MAR) to memory. It is one-way (unidirectional), because only the CPU chooses addresses.

The data bus carries data and instructions between the CPU (the MDR) and memory. It is two-way (bidirectional), because data is both read and written.

The control bus carries control signals from the control unit, such as 'read', 'write' and the clock signal. It is two-way, because devices also send signals back.

3.1 Computer architecture · The explanation · step 4 of 19 · part 2 of 2

The three buses (continued)

!Watch out

Exam answers often say 'the address bus carries data'. It carries addresses only. Data and instructions travel on the data bus.

3.1 Computer architecture · The explanation · step 5 of 19 · part 1 of 4

The fetch–decode–execute cycle

Every instruction goes through the same three stages. Learn the fetch stage in order: it is worth most marks.

Fetch: the address in the PC is copied to the MAR, using the address bus. The PC is incremented (1 is added), so it points to the next instruction. The instruction at that address is sent along the data bus to the MDR. It is then copied from the MDR to the CIR.

3.1 Computer architecture · The explanation · step 5 of 19 · part 2 of 4

The fetch–decode–execute cycle (continued)

Decode: the control unit decodes the instruction in the CIR. It works out what the instruction means and what needs to happen.

Execute: the instruction is carried out. The control unit sends signals on the control bus. If there is a calculation, the ALU does it and the result goes in the ACC. Then the cycle starts again.

3.1 Computer architecture · The explanation · step 5 of 19 · part 3 of 4

The fetch–decode–execute cycle (continued)

e.g.Example
PC = 100. The instruction at address 100 is LOAD 105 (put the value at address 105 into the ACC). Fetch: 100 is copied from PC to MAR → PC becomes 101 → LOAD 105 travels from address 100 to the MDR → copied to the CIR. Decode: the CU sees 'load the value at address 105'. Execute: 105 goes into the MAR → the value at 105 (say 7) comes back on the data bus to the MDR → it is copied to the ACC. ACC = 7. Try it in the toy: its tiny program starts at address 0 (LOAD 5, ADD 6, STORE 7, HALT). Press Step and watch each register change. Notice when the PC goes up by 1.

3.1 Computer architecture · The explanation · step 5 of 19 · part 4 of 4

The fetch–decode–execute cycle (continued)

?Why?

The PC is incremented during fetch, so the CPU always knows where the next instruction is, even while it is busy with the current one.

There is something to try for this step in the IGCSE library.

The explanation · 14 more steps

More on the lesson page

The lesson page has the rest of the explanation, step by step:

  • The instruction set
  • Cores, cache and clock speed
  • Embedded systems
  • Why errors happen
  • Parity check: odd and even
  • Parity byte and parity block
  • Checksum
  • Echo check
  • Check digits
  • Automatic repeat query (ARQ)
  • Be precise, and amend with care
  • The 15-mark scenario question: plan first
  • Model answer in pseudocode and Python
  • How the 15 marks are awarded

Open the lesson page

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Quick quiz · 1 of 3

Which of these is lossy?

  1. A PNG
  2. B JPEG
  3. C ZIP

B. JPEG

JPEG throws away detail. PNG and ZIP give every bit back.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Quick quiz · 2 of 3

A 10 × 10 image at 8 bits per pixel takes…

  1. A 800 bits = 100 bytes
  2. B 8,000 bits
  3. C 80 bytes

A. 800 bits = 100 bytes

10 × 10 × 8 = 800 bits. Divide by 8 for bytes.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Quick quiz · 3 of 3

A packet's header holds…

  1. A The whole file
  2. B Only the data
  3. C The sender's and receiver's addresses and the packet number

C. The sender's and receiver's addresses and the packet number

The header is the label. The payload is the data.

Year 11 · Computer Science · Final revision and the exams · Lesson 2 of 5

Exit ticket

Answer on paper before you go. Then check.

  1. Sending one bit at a time down one wire is…

    A ParallelB SerialC Duplex

    B. Serial Parallel sends several bits at once down several wires.

  2. A walkie-talkie, where only one side can talk at a time, is…

    A Half-duplexB SimplexC Full-duplex

    A. Half-duplex Both ways, but not at once. Full-duplex is both at once, like a phone.